By Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)
This booklet exhibits readers the way to strengthen energy-efficient algorithms and architectures to permit high-definition 3D video coding on resource-constrained embedded units. clients of the Multiview Video Coding (MVC) general face the problem of exploiting its 3D video-specific coding instruments for expanding compression potency on the rate of accelerating computational complexity and, as a result, the power intake. This ebook permits readers to lessen the multiview video coding power intake via together contemplating the algorithmic and architectural degrees. assurance comprises an creation to 3D movies and an intensive dialogue of the present cutting-edge of 3D video coding, in addition to energy-efficient algorithms for 3D video coding and energy-efficient structure for 3D video coding.
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Extra resources for 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures
2009) is composed of two specific accelerators (video decoder and descriptor), one general accelerator (MX), three RISC CPUs, and caches. Woo et al. (2008) describe a 195 mW mobile multimedia SoC with ARM 9, AVC/MPEG decoder, JPEG codec, fully programmable 3D engine, and multiple peripheral interfaces. The heterogeneous multicores approach is the most used in the current set-top boxes, digital TV decoders, and smart mobile devices. It takes advantage of some degree of flexibility along with the performance of specific accelerators.
1). A group of MBs is called slice. The slice can be formed by one or more MBs that may be contiguous or not. One frame is formed by one or more slices. In turn, each slice is classified in one of three different types (here the SI and SP slices are not considered): Intra (I), predictive (P), and bi-predictive (B) slices. 1 is composed of three slices: one contiguous (Slice 0) and two noncontiguous slices (Slices 1 and 2). 264 standard and is directly applicable to the MVC standard. For a better comprehension on the different slice types it is necessary to understand the two basic prediction modes used by the state-of-the-art video encoders: intra-frame and inter-frame prediction.
These techniques consider longer periods and may not cope with severe variations at the MB level. 36 2 Background and Related Works In Fukano et al. (2008) a DVS using dual power supply is used to implement a 65 nm SRAM memory employing three operation modes (1) high speed, (2) low power, and (3) sleep mode. In this work the low power and sleep modes are data retentive avoiding data refetching, but it does not support partial DVS for specific sectors of the SRAM. Yamaoka et al. (2004) present a similar solution employing three operation modes while supporting bank-level DVS.